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Fabricante

ML4804

Power Factor Correction and PWM Controller Combo

Micro Linear Corporation 

ML4804

FUNCTIONAL DESCRIPTION (Continued)

voltage loop error amplifier; stability and transient

response. Optimizing interaction between transient

response and stability requires that the error amplifier’s

open-loop crossover frequency should be 1/2 that of the

line frequency, or 23Hz for a 47Hz line (lowest

anticipated international power frequency). The gain vs.

input voltage of the ML4804’s voltage error amplifier has

a specially shaped nonlinearity such that under steady-

state operating conditions the transconductance of the

error amplifier is at a local minimum. Rapid perturbations

in line or load conditions will cause the input to the

voltage error amplifier (VFB) to deviate from its 2.5V

(nominal) value. If this happens, the transconductance of

the voltage error amplifier will increase significantly, as

shown in the Typical Performance Characteristics. This

raises the gain-bandwidth product of the voltage loop,

resulting in a much more rapid voltage loop response to

such perturbations than would occur with a conventional

linear gain characteristic.

The current amplifier compensation is similar to that of

the voltage error amplifier with the exception of the

choice of crossover frequency. The crossover frequency of

the current amplifier should be at least 10 times that of

the voltage amplifier, to prevent interaction with the

voltage loop. It should also be limited to less than 1/6th

that of the switching frequency, e.g. 16.7kHz for a

100kHz switching frequency.

There is a modest degree of gain contouring applied to the

transfer characteristic of the current error amplifier, to

increase its speed of response to current-loop

perturbations. However, the boost inductor will usually be

the dominant factor in overall current loop response.

Therefore, this contouring is significantly less marked than

that of the voltage error amplifier. This is illustrated in the

Typical Performance Characteristics.

For more information on compensating the current and

voltage control loops, see Application Notes 33 and 34.

Application Note 16 also contains valuable information

for the design of this class of PFC.

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of RT

and CT, which determine the ramp and off-time of the

oscillator output clock:

fOSC

=

tRAMP

1

+ tDEADTIME

(2)

The deadtime of the oscillator is derived from the

following equation:

FHG IKJ tRAMP

= CT

× RT

× In

VREF − 1.25

VREF − 3.75

(3)

at VREF = 7.5V:

tRAMP = CT × RT × 0.51

The deadtime of the oscillator may be determined using:

tDEADTIME

=

2.5V

5.5mA

×

CT

=

450

×

CT

(4)

The deadtime is so small (tRAMP >> tDEADTIME) that the

operating frequency can typically be approximated by:

fOSC

=

1

tRAMP

(5)

EXAMPLE:

For the application circuit shown in the data sheet, with

the oscillator running at:

fOSC

=

100kHz

=

1

tRAMP

Solving for RT x CT yields 1.96 x 10-4. Selecting

standard components values, CT = 390pF, and RT =

51.1kΩ.

The deadtime of the oscillator adds to the Maximum

PWM Duty Cycle (it is an input to the Duty Cycle

Limiter). With zero oscillator deadtime, the Maximum

PWM Duty Cycle is typically 45%. In many applications,

care should be taken that CT not be made so large as to

extend the Maximum Duty Cycle beyond 50%. This can

be accomplished by using a stable 390pF capacitor for CT.

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4804 is straightforward, but

there are several points which should be noted. Foremost

among these is its inherent synchronization to the PFC

section of the device, from which it also derives its basic

timing. The PWM is capable of current-mode or voltage

mode operation. In current-mode applications, the PWM

ramp (RAMP 2) is usually derived directly from a current

sensing resistor or current transformer in the primary of the

output stage, and is thereby representative of the current

flowing in the converter’s output stage. DC ILIMIT, which

provides cycle-by-cycle current limiting, is typically

connected to RAMP 2 in such applications. For voltage-

mode operation or certain specialized applications,

RAMP 2 can be connected to a separate RC timing

network to generate a voltage ramp against which VDC

will be compared. Under these conditions, the use of

voltage feedforward from the PFC buss can assist in line

regulation accuracy and response. As in current mode

operation, the DC ILIMIT input would is used for output

stage overcurrent protection.

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