ML4804 Ver la hoja de datos (PDF) - Micro Linear Corporation
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ML4804 Datasheet PDF : 14 Pages
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FUNCTIONAL DESCRIPTION (Continued)
No voltage error amplifier is included in the PWM stage
of the ML4804, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.
PWM Current Limit
The DC ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.45V. Once this voltage reaches 2.45V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (RRAMP2, CRAMP2), that will have a
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
ML4804
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
CSS
=
t DELAY
×
25µA
1.25V
(6)
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of CSS:
CSS
=
5ms
×
25µA
1.25V
= 100nF
(6a)
Generating VCC
The ML4804 is a voltage-fed part. It requires an external
15V, ±10% (or better) shunt voltage regulator, or some
other VCC regulator, to regulate the voltage supplied to
the part at 15V nominal. This allows low power dissipation
while at the same time delivering 13V nominal gate drive
at the PWM OUT and PFC OUT outputs. If using a Zener
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
RL
C1
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme
11
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