ML2500B Ver la hoja de datos (PDF) - Oki Electric Industry

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ML2500B

Analog-Storage Single-chip Record/Playback LSI with 1M Bit-Cell Flash Memory

Oki Electric Industry 

OKI Semiconductor

FEDL2500BFULL-02

ML2500BTA

Operational Timing at Power-On

To initialize the internal serial interface circuit of ML2500B after power-on, you must input “L” pulse to the

RESET pin at the timing shown below. After this “L” pulse input, the ML2500B enters into standby state

(Command-wait state).

Timing for inputting RESET pulse at Power-on

VDD

RESET(I)

2.7 V

tRST

1 µs

tPWUP

1 ms

PDWN command input

CS

Status

Resetting

Powering Up

Standby (Command-wait)

Power Down

Timing for Power Up and Power Down Operations

ML2500B stops its oscillation circuit to shift to power-down state either by using the PDWN command or by

inputting Low level to the RESET pin. In power-down state, the ML2500B turns into low power consumption

mode.

Two options are available to power up the LSI again after power down by the PDWN command:

1. Input “L” pulse to the RESET pin, or

2. Input Low level to the CS pin.

The following charts show timings for power up and power down operations.

Timing for power-down operation by using the PDWN command

CS(I)

PDWN command input

RESET(I)

tPDWN

100 µs

Status Command-wait

Power Down

tCSWL

1 µs

tRST

1 µs

Power up with CS pin

Power up with RESET pin

tPWUP

1 ms

Powering Up

Command-wait

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