ML2500B Ver la hoja de datos (PDF) - Oki Electric Industry

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ML2500B

Analog-Storage Single-chip Record/Playback LSI with 1M Bit-Cell Flash Memory

Oki Electric Industry 

OKI Semiconductor

FEDL2500BFULL-02

ML2500BTA

Timing for Power-down operation with RESET pin

RESET(I)

Power-down with RESET pin

tPDWNR

100 µs

Status Command-wait

Power Down

Power-up with RESET pin

tPWUP

1 ms

Powering Up

Command-wait

Timing for Record/Playback Operation

1. Timing for Recording Operation

The following chart shows timing for recording operation at 6.4 kHz sampling frequency. It is assumed that the

Start and Stop Addresses are set by the STADR and SPADR commands prior to the REC command input.

CS(I)

Power-up

MON(O)

REC command input

tRECM

tRECR

STOP command input

tSPCM

tSPCR

PDWN command input

RPM

Bit(O)

Status Power-down

10 ms(Typ.)

Command-wait

Erasing

62.5 ms(Typ.)

200 ms(Typ.)

Recording

tPDWN

200 ms(Typ.)

Command-wait Power-down

Dummy Recording

(Note 1) It takes about 210 ms (Typ.) for the LSI to start actual recording after the REC command input, as the

LSI first erase 1 sector before it can start recording.

(Note 2) When recording is stopped by the STOP command, the LSI continues to record until the last address of

the current page is reached. This “lag” recording time is the STOP command of about 62.5 ms (Typ.). Afterwards,

dummy recording is taken place up to the end of the following sector (max. 2 sectors). This dummy recording

takes about 200 ms (Typ.). The dummy recording is given in the device specification and the recording contents

are undefined.

(Note 3) It is recommended to use the power-down mode in order to reduce power consumption when record or

playback are not performed.

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