M95160-DFCS6TG(2014) Ver la hoja de datos (PDF) - STMicroelectronics

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M95160-DFCS6TG
(Rev.:2014)

16-Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Power-up and delivery state

M95160 M95160-W M95160-R M95160-DF

7

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

• Standby power mode,

• deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started),

• not in the Hold condition,

• the Write Enable Latch (WEL) is reset to 0,

• Write In Progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous

power-down (they are non-volatile bits).

7.2

Initial delivery state

The device is delivered with:

• the memory array set to all 1s (each byte = FFh)

• Status register: bit SRWD =0, BP1 =0 and BP0 =0

• Identification page: byte values are Don’t Care.

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