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M58LW128A

128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst) 3V Supply Flash Memories

STMicroelectronics 

Figure 6. Block Addresses

M58LW128A, M58LW128B

M58LW128A, M58LW128B

Word (x16) Bus Width

Address lines A1-A23

7FFFFFh

7F0000h

7EFFFFh

7E0000h

1 Mbit or

64 KWords

1 Mbit or

64 KWords

Total of 128

1 Mbit Blocks

M58LW128B

Double-Word (x32) Bus Width

Address lines A2-A23

(A1 is Don't Care)

3FFFFFh

1 Mbit or

32 KDouble-Words

3F8000h

3F7FFFh

1 Mbit or

32 KDouble-Words

3F0000h

01FFFFh

010000h

00FFFFh

000000h

1 Mbit or

64 KWords

1 Mbit or

64 KWords

00FFFFh

1 Mbit or

32 KDouble-Words

008000h

007FFFh

1 Mbit or

32 KDouble-Words

000000h

Note: Also see Appendix A, Table 28 for a full listing of the Block Addresses

AI06130

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A1-A23). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable must be low when selecting the ad-

dresses.

The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable,

whichever occurs first in a write operation. The ad-

dress latch is transparent when Latch Enable is

low, VIL. The address is internally latched in a pro-

gram or erase operation.

With a x32 Bus Width, WORD = VIH, Address Input

A1 is ignored; the Least Significant Word is output

on DQ0-DQ15 and the Most Significant Word is

output on DQ16-DQ31. With a x16 Bus Width,

WORD = VIL, the Least Significant Word is output

on DQ0-DQ15 when A1 is low, VIL, and the Most

Significant Word is output on DQ0-DQ15 when A1

is high, VIH.

Data Inputs/Outputs (DQ0-DQ31). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a Program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

When Chip Enable and Output Enable are both

low, VIL, the data bus outputs data from the mem-

ory array, the Electronic Signature, the Block Pro-

tection status, the CFI Information or the contents

of the Status Register. The data bus is high imped-

ance when the chip is deselected, Output Enable

is High, VIH, or the Reset/Power-Down signal is

Low, VIL. When the Program/Erase Controller is

active the Ready/Busy status is given on DQ7

while DQ0-DQ6 and DQ8-DQ31 are high imped-

ance.

With a x16 Bus Width, WORD = VIL, DQ16-DQ31

are not used and are high impedance.

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

VIH deselects the memory and reduces the power

consumption to the Standby level, IDD1.

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation. When Output Enable, G, is at VIH

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