M58LW128A Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

M58LW128A

128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst) 3V Supply Flash Memories

STMicroelectronics 

M58LW128A, M58LW128B

Table 3. Synchronous Burst Read Bus Operations

Bus Operation

Step

E G RP K(3) L

B

A1-A23

DQ0-DQ31

Address Latch

VIL X VIH T VIL X Address Input

Read (no address advance)

VIL VIL VIH T X VIH Data Output

Synchronous Burst Read

Pipelined Synchronous

Burst Read

Read (with address advance)

Read Suspend

Read Resume (no address

advance)

VIL VIL VIH T

VIL VIH VIH X

VIL VIL VIH T

X VIL Data Output

X VIH

High Z

X VIH Data Output

Read Resume (with address

advance)

VIL VIL VIH T X VIL Data Output

Read Abort

VIH X VIH X

X

X

High Z

Note: 1. X = Don’t Care, VIL or VIH.

2. M15 = 0, Bit M15 is in the Burst Configuration Register.

3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read

X-Latency

Y-Latency

Address Latch Clock Cycle

Burst Length = 4

Burst Length = 8

8

1

6

10

9

1

7

11

12

1

10

14

13

1

11

15

15

2

11

19

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