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M58LW032A

32 Mbit (2Mb x16, Uniform Block, Burst) 3V Supply Flash Memory

STMicroelectronics 

M58LW032A

Table 4. Burst Configuration Register

Address

Bit

Mnemonic

Bit Name

Reset

Value

Value

Description

0 Synchronous Burst Read

16

M15

Read Select

1

1 Asynchronous Bus Read (default at power-up)

15

M14

Reserved

001 Reserved

010 X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)(1)

14

011 X-Latency = 5, 5-1-1-1, 5-2-2-2

to

M13-M11 X-Latency(2) XXX

12

100 X-Latency = 6, 6-1-1-1, 6-2-2-2

101 X-Latency = 7, 7-1-1-1, 7-2-2-2

110 X-Latency = 8, 8-1-1-1, 8-2-2-2

11

M10

Internal

Clock Divider

X

0 X and Y-Latencies remains as set in M13-M11 and M9

1 Divides internal clock, X and Y-Latencies multiplied by 2

0 Y-Latency = 1

10

M9

Y-Latency(3)

X

1 Y-Latency = 2

9

M8

Valid Data

Ready

X

0 R valid Low during valid Clock edge

1 R valid Low one cycle before valid Clock edge

0 Interleaved

8

M7

Burst Type

X

1 Sequential

7

M6

Valid Clock

Edge

X

0 Falling Clock edge

1 Rising Clock edge

6 to 4

M5-M3

Reserved

001 4 Words

3

to

M2-M0 Burst Length XXX 010 8 Words

1

111 Continuous

Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.

2. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK

is the clock period).

3. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.

4. tSYSTEM MARGIN is the time margin required for the calculation.

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