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M58LW032A

32 Mbit (2Mb x16, Uniform Block, Burst) 3V Supply Flash Memory

STMicroelectronics 

M58LW032A

BUS OPERATIONS

There are 12 bus operations that control the mem-

ory. Each of these is described in this section, see

Tables 2 and 3, Bus Operations, for a summary.

The bus operation is selected through the Burst

Configuration Register; the bits in this register are

described at the end of this section.

On Power-up or after a Hardware Reset the mem-

ory defaults to Asynchronous Latch Enable Con-

trolled Read and Asynchronous Bus Write, no

other bus operation can be performed until the

Burst Control Register has been configured.

The Electronic Signature, CFI or Status Register

will be read in asynchronous mode or single syn-

chronous burst mode.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 3

together with the text below.

Asynchronous Bus Read. Asynchronous Bus

Read operations read from the memory cells, or

specific registers (Electronic Signature, Status

Register, CFI and Block Protection Status) in the

Command Interface. A valid bus operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable,

Output Enable and Latch Enable and keeping

Write Enable High, VIH. The Data Inputs/Outputs

will output the value, see Figure 11, Asynchronous

Bus Read AC Waveforms, and Table 15, Asyn-

chronous Bus Read AC Characteristics, for details

of when the output becomes valid.

Asynchronous Latch Controlled Bus Read.

Asynchronous Latch Controlled Bus Read opera-

tions read from the memory cells or specific regis-

ters in the Command Interface. The address is

latched in the memory before the value is output

on the data bus, allowing the address to change

during the cycle without affecting the address that

the memory uses.

A valid bus operation involves setting the desired

address on the Address Inputs, setting Chip En-

able and Latch Enable Low, VIL and keeping Write

Enable High, VIH; the address is latched on the ris-

ing edge of Address Latch. Once latched, the Ad-

dress Inputs can change. Set Output Enable Low,

VIL, to read the data on the Data Inputs/Outputs;

see Figure 12, Asynchronous Latch Controlled

Bus Read AC Waveforms and Table 16, Asyn-

chronous Latch Controlled Bus Read AC Charac-

teristics for details on when the output becomes

valid.

Note that, since the Latch Enable input is transpar-

ent when set Low, VIL, Asynchronous Bus Read

operations can be performed when the memory is

configured for Asynchronous Latch Enable bus

operations by holding Latch Enable Low, VIL

throughout the bus operation.

Asynchronous Page Read. Asynchronous Page

Read operations are used to read from several ad-

dresses within the same memory page. Each

memory page is 4 Words and has the same A3-

A21, only A1 and A2 may change.

Valid bus operations are the same as Asynchro-

nous Bus Read operations but with different tim-

ings. The first read operation within the page has

identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. See Figure 13, Asynchronous Page

Read AC Waveforms and Table 17, Asynchro-

nous Page Read AC Characteristics for details on

when the outputs become valid.

Asynchronous Bus Write. Asynchronous Bus

Write operations write to the Command Interface

in order to send commands to the memory or to

latch addresses and input data to program. Bus

Write operations are asynchronous, the clock, K,

is don’t care during Bus Write operations.

A valid Asynchronous Bus Write operation begins

by setting the desired address on the Address In-

puts and setting Latch Enable Low, VIL. The Ad-

dress Inputs are latched by the Command

Interface on the rising edge of Chip Enable or

Write Enable, whichever occurs first. The Data In-

puts/Outputs are latched by the Command Inter-

face on the rising edge of Chip Enable or Write

Enable, whichever occurs first. Output Enable

must remain High, VIH, during the whole Asyn-

chronous Bus Write operation. See Figures 14,

and 16, Asynchronous Write AC Waveforms, and

Tables 18 and 19, Asynchronous Write and Latch

Controlled Write AC Characteristics, for details of

the timing requirements.

Asynchronous Latch Controlled Bus Write.

Asynchronous Latch Controlled Bus Write opera-

tions write to the Command Interface in order to

send commands to the memory or to latch ad-

dresses and input data to program. Bus Write op-

erations are asynchronous, the clock, K, is don’t

care during Bus Write operations.

A valid Asynchronous Latch Controlled Bus Write

operation begins by setting the desired address on

the Address Inputs and pulsing Latch Enable Low,

VIL. The Address Inputs are latched by the Com-

mand Interface on the rising edge of Latch Enable,

Chip Enable or Write Enable, whichever occurs

first. The Data Inputs/Outputs are latched by the

Command Interface on the rising edge of Chip En-

able or Write Enable, whichever occurs first. Out-

13/61

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