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M34D64-WDW6 Ver la hoja de datos (PDF) - STMicroelectronics

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M34D64-WDW6 Datasheet PDF : 21 Pages
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M34D64
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 8192 x 8.
Figure 2. Logic Diagram
VCC
3
E0-E2
SCL
WC
M34D64
SDA
VSS
AI02850B
Table 1. Signal Names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
VCC
VSS
Supply Voltage
Ground
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
These devices are compatible with the I2C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 3. SO and TSSOP Connections
M34D64
E0 1
E1 2
8 VCC
7 WC
E2 3
6 SCL
VSS 4
5 SDA
AI02851C
Note: 1. See page 17 (onwards) for package dimensions, and how
to identify pin-1.
2/21

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