M34D64-WDW6 Ver la hoja de datos (PDF) - STMicroelectronics
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M34D64-WDW6
STMicroelectronics
M34D64-WDW6 Datasheet PDF : 21 Pages
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M34D64
data starts to become overwritten in an implemen-
tation dependent way.
The bus master sends from 1 to 32 bytes of data.
If Write Control (WC) is High, the contents of the
addressed top quarter of the memory location are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 5 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
First byte of instruction
with RW = 0 already
decoded by the device
NO ACK
Returned
YES
Next
NO
Operation is
Addressing the
Memory
ReSTART
YES
Send Address
and Receive ACK
STOP
NO
START
YES
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
AI01847C
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory
cells. The maximum Write time (tw) is shown in
Tables 13 and 14, but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 8, is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
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