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M28W320CT09GB1T Datasheet PDF : 42 Pages
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M28W320CT, M28W320CB
Program (PG)
The memory array can be programmed word-by-
word. This instruction uses two write cycles. The
first command written is the Program Set-up com-
mand 40h (or 10h). A second write operation latch-
es the Address and the Data to be written and
starts the P/E.C.
Read operations output the Status Register con-
tent after the programming has started. The Status
Register bit b7 returns ’0’ while the programming
is in progress and ’1’ when it has completed. After
completion the Status register bit b4 returns ’1’ if
there has been a Program Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
turns a ’1’ if VPP is below VPPLK. Programming
aborts if RP goes to VIL. As data integrity cannot
be guaranteed when the program operation is
aborted, the memory location must be erased and
reprogrammed. A Clear Status Register instruc-
tion must be issued to reset b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Double Word Program (DPG)
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when VPP is not at VPPH. The operation can
also be executed if VPP is below VPPH but result
could be uncertain. This instruction uses three
write cycles. The first command written is the Dou-
ble Word Program Set-Up command 30h. A sec-
ond write operation latches the Address and the
Data of the first word to be written, the third write
operation latches the Address and the Data of the
second word to be written and starts the P/E.C.
Read operations output the Status Register con-
tent after the programming has started. The Status
Register bit b7 returns ’0’ while the programming
is in progress and ’1’ when it has completed. After
completion the Status register bit b4 returns ’1’ if
there has been a Program Failure. Status register
bit b1 returns ’1’ if the user is attempting to pro-
gram a protected block. Status Register bit b3 re-
turns a ’1’ if VPP is below VPPLK. Programming
aborts if RP goes to VIL. As data integrity cannot
be guaranteed when the program operation is
aborted, the memory location must be erased and
reprogrammed. A Clear Status Register instruc-
tion must be issued to reset b4, b3 and b1 of the
Status Register.
During the execution of the program by the P/E.C.,
the memory accepts only the RSR (Read Status
Register) and PES (Program/Erase Suspend) in-
structions.
Clear Status Register (CLRS)
The Clear Status Register uses a single write op-
eration which clears bits b1, b3, b4 and b5 to 0. Its
use is necessary before any new operation when
an error has been detected.
The Clear Status Register is executed writing the
command 50h.
Program/Erase Suspend (PES)
Program/Erase suspend is accepted only during
the Program Erase instruction execution. When a
Program/Erase Suspend command is written to
the C.I., the P/E.C. freezes the Program/Erase op-
eration. Program/Erase Resume (PER) continues
the Program/Erase operation. Program/Erase
Suspend consists of writing the command B0h
without any specific address.
The Status Register bit b2 is set to ’1’ (within 5µs)
when the program has been suspended. b2 is set
to ’0’ in case the program is completed or in
progress. The Status Register bit b6 is set to ’1’
(within 30µs) when the erase has been suspend-
ed. b6 is set to ’0’ in case the erase is completed
or in progress. The valid commands while erase is
suspended are: Program/Erase Resume, Pro-
gram, Read Array, Read Status Register, Read
Identifier, CFI Query, Block Protect, Block Unpro-
tect, Block Lock and Protection Program. The user
can protect the Block being erased issuing the
Block Protect, Block Lock or Protection Program
commands. In this case the protection status bit
will change immediately, but when the erase is re-
sumed, the operation will complete The valid com-
mands while program is suspended are: Program/
Erase Resume, Read Array, Read Status Regis-
ter, Read Identifier, CFI Query.
During program/erase suspend mode, the chip
can be placed in a pseudo-stand-by mode by tak-
ing E to VIH This reduces active current consump-
tion. Program/Erase is aborted if RP turns to VIL.
Program/Erase Resume (PER)
If a Program/Erase Suspend instruction was previ-
ously executed, the program/erase operation may
be resumed by issuing the command D0h. The
status register bit b2/b6 is cleared when program/
erase resumes. Read operations output the status
register after the program/erase is resumed.
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