M24512-R, M24512-W, M24512-DR
Figure 6. I2C bus protocol
SCL
SDA
Start
condition
SDA
Input
SDA
Change
Signal description
Stop
condition
SCL
SDA
1
2
3
MSB
Start
condition
7
8
9
ACK
SCL
1
2
3
7
8
9
SDA
MSB
ACK
Stop
condition
AI00792c
Table 2.
Device select code (for memory array)
Device type identifier(1)
Chip Enable address(2) RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
Device select code to access the Identification page (M24512-DR only)
Device type identifier(1)
Chip Enable address(2) RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Doc ID 16459 Rev 19
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