M24512-DFMNTG/K Ver la hoja de datos (PDF) - STMicroelectronics

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M24512-DFMNTG/K

512-Kbit serial I²C bus EEPROM

STMicroelectronics 

Device operation

M24512-R, M24512-W, M24512-DR

3.14

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

After the successful completion of a Read operation, the device’s internal address counter is

incremented by one, to point to the next byte address.

Figure 10. Read mode sequences

Current

Address

Read

ACK

NO ACK

Dev sel

Data out

R/W

Random

Address

Read

ACK

ACK

ACK

ACK

NO ACK

Dev sel *

Byte addr

Byte addr

Dev sel *

Data out

R/W

R/W

Sequential

Current

Read

Sequential

Random

Read

ACK

ACK

Dev sel

Data out 1

R/W

ACK

NO ACK

Data out N

ACK

ACK

ACK

ACK

ACK

Dev sel *

Byte addr

Byte addr

Dev sel *

Data out 1

R/W

R/W

ACK

NO ACK

Data out N

AI01105d

3.15

Random Address Read (in memory array)

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 10) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

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Doc ID 16459 Rev 19

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