LTC4252-1IMS8-TRPBF Ver la hoja de datos (PDF) - Linear Technology

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LTC4252-1IMS8-TRPBF

Negative Voltage Hot Swap Controllers

Linear Technology 

LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

APPLICATIONS INFORMATION

conditions are met. A high-to-low transition in the UV

comparator immediately shuts down the LTC4252, pulls

the MOSFET gate low and resets the latched PWRGD high.

Overvoltage conditions detected by the OV compara-

tor will also pull GATE low, thereby shutting down the

load. However, it will not reset the circuit breaker TIMER,

PWRGD flag or shutdown cooling timer. Returning the

supply voltage to an acceptable range restarts the GATE

pin if all the interlock conditions except TIMER are met.

Only during the initial timing cycle does an OV condition

reset the TIMER.

DRAIN

Connecting an external resistor, RD, to the dual function

DRAIN pin allows VOUT sensing* without it being dam-

aged by large voltage transients. Below 5V, negligible pin

leakage allows a DRAIN low comparator to detect VOUT

less than 2.385V (VDRNL). This condition, together with

the GATE low comparator, sets the PWRGD flag.

If VOUT > VDRNCL, the DRAIN pin is clamped at about

VDRNCL and the current flowing in RD is given by:

IDRN

≈

VOUT

-VDRNCL

RD

(1)

This current is scaled up 8 times during a circuit breaker

fault and is added to the nominal 230μA TIMER current.

This accelerates the fault TIMER pull-up when the MOS-

FET’s drain-source voltage exceeds VDRNCL and effectively

shortens the MOSFET heating duration.

TIMER

The operation of the TIMER pin is somewhat complex as

it handles several key functions. A capacitor CT is used at

TIMER to provide timing for the LTC4252. Four different

charging and discharging modes are available at TIMER:

1) A 5.8μA slow charge; initial timing and shutdown cool-

ing delay.

2) A (230μA + 8 • IDRN) fast charge; circuit breaker delay.

3) A 5.8μA slow discharge; circuit breaker “cool off” and

shutdown cooling.

16

4) Low impedance switch; resets the TIMER capacitor

after an initial timing delay, in UVLO, in UV and in OV

during initial timing.

For initial start-up, the 5.8μA pull-up is used. The low

impedance switch is turned off and the 5.8μA current

source is enabled when the interlock conditions are met.

CT charges to 4V in a time period given by:

t = 4V •CT

5.8μA

(2)

When CT reaches 4V (VTMRH), the low impedance switch

turns on and discharges CT. A GATE start-up cycle begins

and both SS and GATE are released.

CIRCUIT BREAKER TIMER OPERATION

If the SENSE pin detects more than a 50mV drop across

RS, the TIMER pin charges CT with (230μA + 8 • IDRN). If

CT charges to 4V, the GATE pin pulls low and the LTC4252-1

latches off while the LTC4252-2 starts a shutdown cooling

cycle. The LTC4252-1 remains latched off until the UV

pin is momentarily pulsed low or TIMER is momentarily

discharged low by an external switch or VIN dips below

UVLO and is then restored. The circuit breaker timeout

period is given by:

t = 4V •CT

230μA +8 •IDRN

(3)

If VOUT < 5V, an internal PMOS device isolates any DRAIN

pin leakage current, making IDRN = 0μA in Equation (3).

If VOUT > VDRNCLduring the circuit breaker fault period,

the charging of CT accelerates by 8 • IDRN of Equation (1).

Intermittent overloads may exceed the 50mV threshold at

SENSE, but, if their duration is sufficiently short, TIMER

will not reach 4V and the LTC4252 will not shut the external

MOSFET off. To handle this situation, the TIMER discharges

CT slowly with a 5.8μA pull-down whenever the SENSE

voltage is less than 50mV. Therefore, any intermittent

overload with VOUT > 5V and an aggregate duty cycle of

*VOUT as viewed by the MOSFET; i.e., VDS.

425212fd

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