LTC4252-1IMS8-TRPBF Ver la hoja de datos (PDF) - Linear Technology

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LTC4252-1IMS8-TRPBF

Negative Voltage Hot Swap Controllers

Linear Technology 

LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

OPERATION

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the

supply bypass capacitors can draw huge transient currents

from the power bus as they charge. The flow of current

damages the connector pins and glitches the power bus,

causing other boards in the system to reset. The LTC4252

is designed to turn on a circuit board supply in a controlled

manner, allowing insertion or removal without glitches or

connector damage.

Initial Start-Up

The LTC4252 resides on a removable circuit board and

controls the path between the connector and load or power

conversion circuitry with an external MOSFET switch (see

Figure 1). Both inrush control and short-circuit protection

are provided by the MOSFET.

A detailed schematic for the LTC4252A is shown in Figure 2.

– 48V and –48RTN receive power through the longest con-

nector pins and are the first to connect when the board is

inserted. The GATE pin holds the MOSFET off during this

time. UV and OV determine whether or not the MOSFET

should be turned on based upon internal high accuracy

thresholds and an external divider. UV and OV do double

duty by also monitoring whether or not the connector is

seated. The top of the divider detects –48RTN by way of

a short connector pin that is the last to mate during the

insertion sequence.

LONG

– 48RTN

LONG

– 48V

BACKPLANE

PLUG-IN BOARD

LTC4252 +

+

+

CLOAD

ISOLATED

DC/DC

CONVERTER

MODULE

–

–

LOW

VOLTAGE

CIRCUITRY

4252-1/2 F01

Figure 1. Basic LTC4252 Hot Swap Topology

12

Interlock Conditions

A start-up sequence commences once these “interlock”

conditions are met.

1. The input voltage VIN exceeds VLKO (UVLO).

2. The voltage at UV > VUVHI.

3. The voltage at OV < VOVLO.

4. The (SENSE – VEE) voltage is < 50mV (VCB).

5. The voltage at SS is < 0.2V (20 • VOS).

6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL).

7. The voltage at GATE is < 0.5V (VGATEL).

The first three conditions are continuously monitored and

the latter four are checked prior to initial timing or GATE

ramp-up. Upon exiting an OV condition, the TIMER pin

voltage requirement is inhibited. Details are described in

the Applications Information, Timing Waveforms section.

TIMER begins the start-up sequence by sourcing 5.8μA

into CT. If VIN, UV or OV falls out of range, the start-up

cycle stops and TIMER discharges CT to less than 1V, then

waits until the aforementioned conditions are once again

met. If CT successfully charges to 4V, TIMER pulls low

and both SS and GATE pins are released. GATE sources

58μA (IGATE), charging the MOSFET gate and associated

capacitance. The SS voltage ramp limits VSENSE to control

the inrush current. PWRGD pulls active low when GATE is

within 2.8V of VIN and DRAIN is lower than VDRNL.

LONG

– 48RTN

DIN+

DDZ13B**

RIN

3 × 1.8k IN SERIES

1/4W EACH

CLOAD +

100μF

SHORT R1

392k

1%

C1

10nF

CIN

1μF

OV

VIN

UV

LTC4252A-1

TIMER

SS

DRAIN

CSS VEE SENSE GATE

R2

68nF

30.1k

1%

CT

0.68μF

CC

RC

10Ω

10nF

LONG

– 48V

RS

Q1

**DIODES, INC

0.02Ω

†RECOMMENDED FOR HARSH ENVIRONMENTS

IRF530S

RD

1M

425212 F02

Figure 2. –48V, 2.5A Hot Swap Controller

425212fd

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