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HT46R14A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R14A

PPG0C: PPG0 timer prescaler rate bits

P0PSC2 P0PSC1 P0PSC0 Prescaler Stage Definition

0

0

0

P0fS=fSYS

0

0

1

P0fS=fSYS/2

0

1

0

P0fS=fSYS/4

0

1

1

P0fS=fSYS/8

1

0

0

P0fS=fSYS/16

1

0

1

P0fS=fSYS/32

1

1

0

P0fS=fSYS/64

1

1

1

P0fS=fSYS/128

The P0SPEN bit will enable or disable the PISP trigger stop control of PPG0. If this bit is enabled, the PPG0 stop in-

put will be triggered by a falling edge on PISP. The PISP signal may be sourced from either C0VO, PC2 or INT1, de-

termined by the PIE bit, which is bit0 of the PPG1C register. The P0RSEN bit will enable or disable the C1VO trigger

restart control of PPG0. If this bit is enabled, the PPG0 timer restart input will be triggered by C1VO. The status of

C0VO or C1VO can be read by setting PC2 or PC3 to be an input pin when Comparator 0 or Comparator 1 is enabled.

P0SPEN

Description

0

Disables the PISP trigger stop function of PPG0. In this case the PPG0 module output can only be

stopped using software control (P0ST).

1

Enables the PISP trigger stop function of PPG0. In this case the PPG0 module can be stopped by a

PISP falling edge trigger or by software control. (P0ST bit is cleared to ²0²).

P0RSEN

Description

0

Disables the C1VO trigger restart function of PPG0. In this case the PPG0 module output can only be

restarted using software control (P0ST).

1

Enables the C1VO triggerr restart function of PPG0. In this case the PPG0 module output can be re-

started by a C1VO falling edge trigger or by software control. (P0ST is set to ²1²)

The P0ST bit is a software trigger bit, if this bit is set to ²1², the PPG0 timer will start counting and will be cleared when

a PPG0 timer overflow occurs or if the PPG0 timer stops counting. If this bit is cleared to ²0², the PPG0 timer will stop

counting. When the PPG timer is counting and if a falling edge is generated from C1VO, PC3 or if the software control

bit, P0ST, is set, the PPG0 timer counter will not be affected, therefore a re-trigger signal from C1V0, PC3 or P0ST

will have no effect. The P0ST bit can also be used as a status bit for the PPG0 timer output.

The PPG0 module output pulse active level is decided by P0LEV bit a configuration option, if cleared to ²0², the PPG0

output will be defined as an active high output, if the P0LEV bit is set to ²1², the PPG0 output will be defined as an active

low output.

Another function, which enables the point when the PPG0 timer starts counting and if it is to be synchronised with the

system clock or not is determined by a configuration option.

· PPG1C control register

Bit No.

7

6

5

4

3

2

1

0

PPG1C (22H)

P1ST P1RSEN P1SPEN P1PSC2 P1PSC1 P1PSC0

¾

PIE

POR value

0

0

0

0

0

0

¾

0

PIE: PPG input exchange bit (0=disable, 1=Enable).

P1PSC2, P1PSC1, P1PSC0: These three bits select the PPG1 timer prescaler rate.

P1SPEN: Enables or disables stopping the PPG1 timer using INT0 trigger input (0=disable, 1=enable).

P1RSEN: Enables or disables restarting the PPG1 timer using PIRS trigger input (0=disable, 1=enable).

P1ST: PPG1 software trigger bit. (0=Stop PPG1, 1=Restart PPG1)

The PIE bit is used as C0VO and INT1 exchange bit. When PIE bit is reset to 0, the PISP signal comes from INT1 and

the PIRS signal comes from C0VO. When PIE bit is set to 1, the PISP signal comes from C0VO and the PIRS signal

comes from INT1.

Rev. 1.00

20

August 3, 2007

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