HT46R14A Ver la hoja de datos (PDF) - Holtek Semiconductor
Número de pieza
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HT46R14A Datasheet PDF : 49 Pages
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HT46R14A
The P1SPEN and P1RSEN should be disabled before setting the PIE bit.
PPG1C: PIE; C0VO and INT1 exchange bit
PIE
Description
0
The PISP signal is sourced from INT1 and the PIRS signal is sourced from C0VO.
1
The PISP signal is sourced from C0VO and the PIRS signal is sourced from INT1.
Bits2~4 of the PPG1 control register, PPG1C, can be used to define the pre-scaling stages of the PPG1 timer counter
clock.
PPG1C: PPG1 timer prescaler rate bits
P1PSC2
0
0
0
0
1
1
1
1
P1PSC1
0
0
1
1
0
0
1
1
P1PSC0
0
1
0
1
0
1
0
1
Prescaler Stage Definition
P1fS=fSYS
P1fS=fSYS/2
P1fS=fSYS/4
P1fS=fSYS/8
P1fS=fSYS/16
P1fS=fSYS/32
P1fS=fSYS/64
P1fS=fSYS/128
The P1SPEN is the PPG1 timer Off enable or disable bit using INT0 trigger input, if this bit is enabled, the PPG1 stop-
ping input can be triggered by INT0 falling edge. The P1RSEN is the PPG1 restarting enable or disable bit using trig-
ger input, if this bit is enabled, the PPG1 timer restarting input can be triggered by PIRS falling edge. The PIRS signal
may come from C0VO, PC2 or INT1, determined by PIE (bit0 of the PPG1C). User can read the status of C0VO or
C1VO by setting the PC2 or PC3 as an input pin when Comparator 0 or Comparator 1 is enabled.
P1SPEN
Description
0
Disable stopping the PPG1 timer using INT0 trigger input. PPG1 module output can be stopped by
software control (P1ST) only.
Enable stopping the PPG0 timer using INT0 trigger input. PPG0 module output can be stopped by
1
INT0 falling edge trigger or software control (P1ST bit is cleared to ²0²).
P1RSEN
Description
0
Disable restarting the PPG1 timer using PIRS trigger input. PPG1 module output can be restarted by
software control (P1ST) only
Enable restarting the PPG1 timer using PIRS trigger input. PPG1 module output can be restarted by
1
PIRS (C0VO or INT1) falling edge trigger or software control (P1ST is set to ²1²)
The P1ST bit is a software trigger bit, if this bit is set to ²1², the PPG1 timer will start counting and will be cleared when
a PPG1 timer overflow occurs or if the PPG1 timer stops counting. If this bit is cleared to ²0², the PPG1 timer will stop
counting. When the PPG timer is counting and if a falling edge is generated from PIRS or if the software control bit,
P1ST, is set, the PPG1 timer counter will not be affected, therefore a re-trigger signal from PIRS or P1ST will have no
effect. The P1ST bit can also be used as a status bit for the PPG1 timer output.
The PPG1 module output pulse active level is decided by P1LEV bit a configuration option, if cleared to ²0², the PPG1
output will be defined as an active high output, if the P1LEV bit is set to ²1², the PPG1 output will be defined as an active
low output.
Another function, which enables the point when the PPG timer starts counting and if it is to be synchronised with the
system clock or not is determined by a configuration option.
Rev. 1.00
21
August 3, 2007
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