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HT46R14A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R14A

Watchdog Timer - WDT

The WDT clock source is implemented using a dedi-

cated internal RC oscillator (WDT oscillator) or by the in-

struction clock, which is the system clock divided by 4.

The choice of which one is used is determined by a

configuration option. This timer is designed to prevent a

software malfunction or a sequence jumping to an un-

known location with unpredictable results. The

Watchdog Timer can be disabled by a configuration op-

tion. If the Watchdog Timer is disabled, all instructions

relating to the WDT result in no operation.

The WDT clock source will be subsequently divided by

either 213, 214 , 215 or 216, determined by a configuration

option, to get the actual WDT time-out period. Using the

internal WDT clock source, the minimum WDT time-out

period is about 600ms. This time-out period may vary

with temperature, VDD and process variations. By se-

lecting appropriate WDT options, longer time-out peri-

ods can be implemented. If the WDT time-out is

selected to be fS/216, then a maximum time-out period of

about 4.7s can be achieved.

If the WDT oscillator is disabled, the WDT clock may still

be sourced from the instruction clock and operate in the

same manner except that in the Power-down mode the

WDT will stop counting and lose its protecting purpose.

In this situation the device can only be restarted by ex-

ternal logic. If the device operates in a noisy environ-

ment, using the internal WDT oscillator is strongly

recommended, since the Power-down mode will stop

the system clock.

The WDT overflow under normal operation will initialise a

device reset and set the status bit TO. In the Power-down

mode, the overflow will initialise a warm reset where only

the program counter and stack pointer are reset to 0. To

clear the WDT contents, three methods are adopted; ex-

ternal reset (a low level to RES), software instructions, or a

HALT instruction. The software instructions include CLR

WDT and the other set - CLR WDT1 and CLR WDT2. Of

these two types of instruction, only one can be active de-

pending on the options - ²CLR WDT times selection op-

tion². If the ²CLR WDT² is selected (i.e. CLRWDT times

equal 1), any execution of the CLR WDT instruction will

clear the WDT. If the ²CLR WDT1² and ²CLR WDT2² op-

tion is selected (i.e. CLRWDT times equal two), these two

instructions must be executed to clear the WDT, other-

wise, the WDT will reset the chip due to a time-out.

Power Down Operation - HALT

The Power-down mode is entered by the execution of a

²HALT² instruction and results in the following:

· The system oscillator will be turned off but the WDT

oscillator will keep running, if the WDT is enabled and

if its clock is sourced from the internal WDT oscillator.

· The contents of the Data Memory and registers

remain unchanged.

· The WDT will be cleared and will start counting again,

if the WDT clock is sourced from the internal WDT

oscillator.

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the Power-down mode by means

of an external reset, an interrupt, an external falling

edge signal on port A or a WDT overflow. An external re-

set causes a device initialisation and the WDT overflow

performs a ²warm reset². After the TO and PDF flags

are examined, the reason for the device reset can be de-

termined.

The PDF flag is cleared by a system power-up or exe-

cuting the ²CLR WDT² instruction and is set when exe-

cuting the ²HALT² instruction. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the program counter and the stack pointer, the

other circuits will maintain their original status.

A port A wake-up and interrupt methods can be consid-

ered as a continuation of normal execution. Each bit in

port A can be independently selected to wake up the de-

vice, setup via configuration options. Awakening from

an I/O port stimulus, the program will resume execution

at the next instruction. If it is awakening from an inter-

rupt, two sequences may occur. If the related interrupt is

disabled or the interrupt is enabled but the stack is full,

the program will resume execution at the next instruc-

tion. If the interrupt is enabled and the stack is not full,

the regular interrupt response takes place. If an interrupt

request flag is set to ²1² before entering the

Power-down mode, the wake-up function of the related

interrupt will be disabled. Once a wake-up event occurs,

it takes 1024 system clock periods to resume normal op-

S y s te m C lo c k /4

W DT

O SC

M a s k fs

o p tio n

s e le c t

W D T C le a r

D iv id e r

fs/2 8

W D T P r e s c a le r

M a s k O p tio n

Watchdog Timer

T im e - o u t R e s e t

fs/2 1 6

fs/2 1 5

fs/2 1 4

fs/2 1 3

Rev. 1.00

12

August 3, 2007

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