PEB2466-HV1.2 Ver la hoja de datos (PDF) - Infineon Technologies

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PEB2466-HV1.2

Four Channel Codec Filter with PCM- and µ-Controller Interface SICOFI®4-µC

Infineon Technologies 

PEB 2466

General Description

1.3 Pin Definition and Functions (cont’d)

Pin No. Symbol

25

TCA

23

RESET

22

MCLK

17

CS

18

DCLK

19

DIN

20

DOUT

33

CHCLK1

16

CHCLK2

34

INT12

15

INT34

Input (I)

Output (O)

O

I

I

I

I

I

O

O

O

O

O

Function

PCM-interface: Transmit control output A, is active if

data is transmitted via DXA, active low, open drain

Reset input - forces the device to default mode,

active low

Master clock input, 1536, 2048, 4096 or 8192 kHz,

synchronous to FSC, must be available if the

SICOFI-4-µC is used

µ-Controller interface: chip select enable to read or

write data, active low

µ-Controller interface: data clock, shifts data from or

to device, the maximum clock rate is 8192 kHz

µ-Controller interface: control data input pin, DCLK

determines the data rate

µ-Controller interface: control data output pin, DCLK

determines the data rate, DOUT is high ‘Z’ if no data

is transmitted from the SICOFI-4-µC

Chopper Clock output, provides a programmable

(2 … 28 ms) output signal (synchronous to MCLK)

Chopper Clock output, provides a 256, or 512 or

16384 kHz signal, is synchronous to MCLK

Interrupt output pin for channel 1 and 2, active high

Interrupt output pin for channel 3 and 4, active high

Semiconductor Group

11

02.97

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