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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Figure 3. Expander Product Terms

to Macrocell Array

8 or 20

Dedicated

Inputs

24 Programmable

Macrocell

Interconnect Signals Feed backs

(Multi-LAB Devices Only)

32 or 64

Expander

Product Terms

Expanders are fed by all signals in the LAB. One expander can feed all

macrocells in the LAB or multiple product terms in the same macrocell.

Since expanders also feed the secondary product terms of each macrocell,

complex logic functions can be implemented without using additional

macrocells. Expanders can also be cross-coupled to build additional

flipflops, latches, or input registers. A small delay (tSEXP) is incurred

when shared expanders are used.

Programmable Interconnect Array

The higher-density MAX 5000 devices—EPM5064, EPM5128, EPM5130,

and EPM5192—use a programmable interconnect array (PIA) to route

signals between the various LABs. The PIA, which is fed by all macrocell

and I/O pin feedbacks, routes only the signals required for implementing

logic in an LAB. While the routing delays of channel-based routing

schemes in masked or field-programmable gate arrays (FPGAs) are

cumulative, variable, and path-dependent, the MAX 5000 PIA has a fixed

delay. The PIA thus eliminates skew between signals and makes timing

performance easy to predict.

I/O Control Blocks

Each LAB has an I/O control block that allows each I/O pin to be

individually configured for input, output, or bidirectional operation. See

Figure 4. The I/O control block is fed by the macrocell array. A dedicated

macrocell product term controls a tri-state buffer, which drives the I/O

pin.

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Altera Corporation

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