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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Macrocells

The MAX 5000 macrocell consists of a programmable logic array and an

independently configurable register (see Figure 2). The register can be

programmed to emulate D, T, JK, or SR operation, as a flow-through latch,

or bypassed for combinatorial operation. Combinatorial logic is

implemented in the programmable logic array, in which three product

terms that are ORed together feed one input to an XOR gate. The second

input to the XOR gate is used for complex XOR arithmetic logic functions

and for De Morgan’s inversion. The output of the XOR gate feeds the

programmable register or bypasses it for combinatorial operation.

Figure 2. MAX 5000 Device Macrocell

Logic Array

Output Enable

Preset

Array Clock

Clear

Global Clock

(One Per LAB)

Programmable

Register

PRN

DQ

CLRN

to I/O

Control

Block

Macrocell Feedback

I/O Feedback

8 or 20

24 Programmable

32 or 64

Dedicated Interconnect Signals

Expander

Inputs (Multi-LAB Devices Only) Product Terms

Additional product terms—called secondary product terms—are used to

control the output enable, preset, clear, and clock signals. Preset and clear

product terms drive the active-low asynchronous preset and

asynchronous clear inputs to the configurable flipflop. The clock product

term allows each register to have an independent clock and supports

positive- and negative-edge-triggered operation. Macrocells that drive an

output pin can use the output enable product term to control the active-

high tri-state buffer in the I/O control block.

The MAX 5000 macrocell configurability makes it possible to efficiently

integrate complete subsystems into a single device.

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Altera Corporation

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