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EPM5032-15

Programmable Logic Device Family

Altera Corporation 

MAX 5000 Programmable Logic Device Family Data Sheet

Functional

Description

This section provides a functional description of MAX 5000 EPLDs, which

have the following architectural features:

s Logic array blocks

s Macrocells

s Clocking options

s Expander product terms

s Programmable interconnect array

s I/O control blocks

The MAX 5000 architecture is based on the concept of linking high-

performance, flexible logic array modules called logic array blocks

(LABs). Multiple LABs are linked via the programmable interconnect

array (PIA), a global bus that is fed by all I/O pins and macrocells. In

addition to these basic elements, the MAX 5000 architecture includes 8 to

20 dedicated inputs, each of which can be used as a high-speed, general-

purpose input. Alternatively, one of the dedicated inputs can be used as a

high-speed global clock for registers.

Logic Array Blocks

MAX 5000 EPLDs contain 1 to 12 LABs. The EPM5032 has a single LAB,

while the EPM5064, EPM5128, EPM5130, and EPM5192 contain multiple

LABs. Each LAB consists of a macrocell array and an expander product-

term array. See Figure 1. The number of macrocells and expanders in the

arrays varies with each device.

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Altera Corporation

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