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EM785841M Ver la hoja de datos (PDF) - ELAN Microelectronics

Número de pieza
componentes Descripción
Fabricante
EM785841M
EMC
ELAN Microelectronics EMC
EM785841M Datasheet PDF : 45 Pages
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EM785840/5841/5842
8-bit Micro-controller
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
3.58MHz, 14.3MHz
PLL circuit
CLK2 ~ CLK0
ENPLL
1
switch
0
System clock
Sub-clock
32.768kHz
Fig.4 The relation between 32.768kHz and PLL
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!
Next table show the status after wake-up and the wake-up sources list.
Wakeup signal
SLEEP mode
TCC time out
IOCF bit0=1
RA(7,6)=(0,0)
+ SLEP
No function
COUNTER1 time out No function
IOCF bit1=1
WDT time out
Reset and jump to
address 0
PORT7 (0,1,3)
Reset and Jump to
address 0
PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger (controlled
by CONT register bit7).
PORT71 's wakeup function is controlled by IOCF bit 4. It’s falling edge trigger.
PORT73 's wakeup function is controlled by IOCF bit 5. It is falling edge trigger.
PAGE1,2 : (undefined) not allowed to use
PAGE3 (DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
3
2
1
0
X
X
X
X
X
X PWM2[9] PWM2[8]
-
-
-
-
-
-
R/W-0 R/W-0
Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM1 output to stay at high until the value matches with TMR1.
Bit 2 ~ Bit 7 : (undefined) not allowed to use
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
13
2004/11/10 V1.2

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