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EM785841M

8-BIT MICRO-CONTROLLER

ELAN Microelectronics 

EM785840/5841/5842

8-bit Micro-controller

R7 (PORT7 I/O data, ADC, Duty cycle of PWM )

PAGE0 (PORT7 I/O data register)

7

6

5

4

3

2

1

0

X

P76

P75

P74

P73

X

P71

P70

-

R/W

R/W

R/W

R/W

-

R

R/W

Bit0 (P70): PORT70 is a multi-function pin. In Crystal mode, by setting P70S in code option, PORT70 will be

general purpose IO or PLLC. Please do not enable PLL function if PORT70 defined to IO. In IRC or ERIC

mode, this pin will defined to PORT70 and P70S will be ignored. P70 is PORT70 I/O data register and user

can use IOC register to define input or output each bit.

Bit1 (P71): PORT71 is shared with /RESET pin. By setting P71S in code option, PORT71 will defined to INPUT

pin or /RESET pin. This register is a read only bit. P71 dose not support internal pull high function. If user

want to use P71 interrupt, external pull high is necessary.

Bit3 ~ Bit6 (P73 ~ P76): 4 - bit PORT7 I/O data register

User can use IOC register to define input or output each bit.

PAGE1 (ADC resolution selection bit and ADC MSB output data)

7

6

5

4

3

2

1

0

X

X

AD9 AD8

X

ADRES

X

X

-

-

R

R

-

R/W-0

R

R

Bit 0~Bit 1: Undefined register. These two bits are not allowed to use. These bits must clear to 0.

Bit 2(ADRES) : Resolution selection for ADC

0 Î ADC is 8-bit resolution

When 8-bit resolution is selected, the most significant(MSB) 8-bit data output of the internal 10-bit ADC

will be mapping to RB PAGE1 so R7 PAGE1 bit 4 ~5 will be of no use.

1 Î ADC is 10-bit resolution

When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapping

to RB PAGE1 and R7 PAGE1 bit 4 ~5.

Bit 3 : (undefined) not allowed to use

Bit 4 ~ Bit 5(AD8 ~ AD9) : The most significant 2 bit of 10-bit ADC conversion output data

Combine there two bits and RB PAGE1 as complete 10-bit ADC conversion output data.

Bit 6 ~ Bit 7 : (undefined) not allowed to use

PAGE2 : (undefined) not allowed to use

PAGE3 (DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM)

7

6

5

4

3

2

1

0

X

X

X

X

X

X PWM1[9] PWM1[8]

-

-

-

-

-

-

R/W-0 R/W-0

Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant two bits of PWM1 Duty Cycle

Bit 2 ~ Bit 7 : Unused.

R8 (Data RAM address, PWM1 period)

PAGE0: (undefined) not allowed to use

PAGE1: (undefined) not allowed to use

PAGE2: (undefined) not allowed to use

PAGE3 (PRD1: Period of PWM)

7

6

5

4

3

2

1

0

PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

The content of this register is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the

period.

__________________________________________________________________________________________________________________________________________________________________

* This specification is subject to change without notice.

11

2004/11/10 V1.2

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