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DS2407

Dual Addressable Switch Plus 1K–Bit Memory

Dallas Semiconductor -> Maxim Integrated 

DS2407

TWO–CHANNEL WRITE Figure 9C

td1 15 µs < td1 < 60 µs

200 ns < td0 < 300 ns

1–WIRE

A1

B1

A2

B2

A3

B3

A4

B4

SYNCHRONOUS MODE

PIO–A

A1

A2

A3

A4

PIO–B

B1

ASYNCHRONOUS MODE

PIO–A

A1

PIO–B

B1

B2

B3

B4

A2

A3

A4

B2

B3

B4

1–WIRE BUS SYSTEM

The 1–Wire bus is a system which has a single bus mas-

ter and one or more slaves. In all instances, the DS2407

is a slave device. The bus master is typically a micro-

controller. The discussion of this bus system is broken

down into three topics: hardware configuration, transac-

tion sequence, and 1–Wire signaling (signal type and

timing). A 1–Wire protocol defines bus transactions in

terms of the bus state during specified time slots that are

initiated on the falling edge of sync pulses from the bus

master. For a more detailed protocol description, please

refer to Chapter 4 of the Book of DS19xx iButton Stan-

dards.

HARDWARE CONFIGURATION

The 1–Wire bus has only a single line by definition; it is

important that each device on the bus be able to drive it

at the appropriate time. To facilitate this, each device

attached to the 1–Wire bus must have an open drain

connection or 3–state outputs. The DS2407 is an open

drain part with an internal circuit equivalent to that

shown in Figure 10. The bus master can be the same

equivalent circuit. If a bidirectional pin is not available,

separate output and input pins can be tied together.

The bus master requires a pull–up resistor at the master

end of the bus, with the bus master circuit equivalent to

the one shown in Figures 11a and 11b. The value of the

pull–up resistor should be approximately 5kΩ for short

line lengths. The interface between bus master and

1–Wire bus may be reduced to a single pull–up resistor

(open drain master) or two resistors plus transistor

(TTL–type master) if the EPROM section of the DS2407

is already programmed before the final installation.

A multidrop bus consists of a 1–Wire bus with multiple

slaves attached. The 1–Wire bus has a maximum data

rate of 16.3k bits per second. If the bus master is also

required to perform programming of the EPROM por-

tions of the DS2407, a programming supply capable of

delivering up to 10 milliamps at 12 volts for 480 µs is

required. Non–EPROM devices cannot be present dur-

ing programming. The idle state for the 1–Wire bus is

high. If, for any reason, a transaction needs to be sus-

pended, the bus MUST be left in the idle state if the

transaction is to resume. If this does not occur and the

bus is left low for more than 120 µs, one or more of the

devices on the bus may be reset. If the 1–Wire bus

remains low for more than 5 ms and the DS2407 is not

powered externally it may lose its current status and

switch off both PIOs.

TRANSACTION SEQUENCE

The sequence for accessing the DS2407 via the 1–Wire

port is as follows:

• Initialization

• ROM Function Command

• Memory Function Command

• Read Memory/Write Memory or Channel Access

012099 18/31

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