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DS2407

Dual Addressable Switch Plus 1K–Bit Memory

Dallas Semiconductor -> Maxim Integrated 

DS2407

ter immediately during the same time slot while the data

bit from channel B follows with the next time slot which

does not sample the PIOs. Both channels will be

sampled again with the time slot that follows the trans-

mission of the data bit from PIO–B (Figure 9b).

When writing in the asynchronous mode, each channel

will change its status independently of the other. The

change of status occurs with the same timing relations

as for communication with one channel. However, every

second write time slot addresses the same channel.

The first time slot is directed to channel A, the second to

channel B, the next to channel A and so on. As a conse-

quence, in asynchronous mode both PIOs can never

change their status at the same time. When writing in

the synchronous mode, both channels operate

together. After the new values for both channels have

arrived at the DS2407 the change of status at both chan-

nels occurs with the same timing relations as for com-

munication with one channel. As with the asynchronous

mode, every second write time slot contains data for the

same channel. The first time slot addresses channel A,

the second channel B and so on. Depending on the data

values, in the synchronous mode both PIOs can change

their status at the same time (Figure 9c). In any of these

cases, the information of channel A and channel B will

appear alternating on the 1–Wire line, always starting

with channel A. By varying the idle–time between time

slots on the 1–Wire line one has full control over the time

points of sampling and the waveforms generated at the

PIO–pins when writing to the device.

The TOG bit of Channel Control Byte 1 specifies if one is

always reading or writing (TOG = 0) or if one is going to

change from reading to writing or vice versa after every

data byte that has been sent to or received from the

DS2407 (TOG = 1). When accessing one channel, one

byte is equivalent to eight reads from or writes to the

selected PIO pin. When accessing two channels, one

byte is equivalent to four reads or writes from/to each

channel.

The initial mode (reading or writing) for accessing the

PIO channels is specified in the IM bit. For reading, IM

has to be set to 1, for writing IM needs to be 0. If the TOG

bit is set to 0, the device will always read or write as spe-

cified by the IM bit. If TOG is 1, the device will use the

setting of IM for the first byte to be transmitted and will

alternate between reading and writing after every byte.

Figure 7c illustrates the effect of TOG and IM for one–

channel as well as for two–channel operation.

Bit 7 of the Channel Control Byte 1 allows resetting of

the activity latch of each channel. The activity latch is set

with the first negative or positive edge detected on its

associated PIO channel. Both activity latches are

cleared simultaneously if bit 7 of the Channel Control

Byte 1 is 1. The activity latches are not changed if this bit

is 0.

Channel Control Byte 1 also controls the internal CRC

generator to safeguard data transmission between the

bus master and the DS2407 for channel access. It does

not affect reading from or writing to the memory sections

of the DS2407. The CRC control bits (bit 0 and bit 1) can

be set to create and protect data packets that have the

size of 8 bytes or 32 bytes. If desired, the device can

safeguard even single bytes by a 16–bit CRC. This set-

ting, however, is recommended only if the data is limited

to one byte since it would reduce the sampling rate to

one third of the maximum possible value.

The CRC control codes are as follows:

CRC1

0

0

1

1

CRC0

0

1

0

1

CRC disabled (no CRC at all)

CRC after every byte

CRC after 8 bytes

(status page size)

CRC after 32 bytes

(data page size)

The CRC provides a high level of data safeguarding and

is more efficient for verification than “read after write”. A

detailed description of CRCs is found in the “Book of

DS19xx iButton Standards”. If the CRC is disabled, the

CRC–related sections in the flow chart are skipped.

Channel Control Byte 2 is reserved for future develop-

ment. The bus master should always send an FFh for

the second Channel Control Byte.

The Channel Info byte (Figure 8) which the bus master

receives after the Channel Control bytes have been

transmitted indicates the status of the channel flip–

flops, the PIO pins, the activity latches as well as the

availability of channel B and external power supply.

Reading 0 for both the channel flip–flop and the sensed

level indicates that the output transistor of the PIO is

pulling the node low. To be able to read from a PIO chan-

nel, the output transistor needs to be non–conducting,

which is equivalent to a 1 for the channel flip–flop. Sam-

pling the level of PIO A and B is done at the same time

(synchronous) for the Channel Info Byte. If channel B is

012099 15/31

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