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DS2404 Datasheet PDF : 28 Pages
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DS2404
Alarm Registers
The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same
manner. When the value of a given counter equals the value in its associated alarm register, the
appropriate flag bit is set in the status register. If the corresponding interrupt enable bit(s) in the status
register is set, an interrupt is generated. If a counter and its associated alarm register are write protected
when an alarm occurs, access to the device becomes limited. (See “Status/Control”, “Interrupts”, and the
“Programmable Expiration” sections.)
STATUS/CONTROL REGISTERS
The status and control registers are the first two bytes of page 16 (see “Memory Map”, Figure 4).
Status Register
7
6
5
4
3
2
1
0
X
X
CCE
ITE
RTE
CCF
ITF
RTF 0200h
Don’t care bits
Read Only
0 RTF Real-time clock alarm flag
1 ITF Interval timer alarm flag
2 CCF Cycle counter alarm flag
When a given alarm occurs, the corresponding alarm flag is set to a logic 1. The alarm flag(s) is cleared
by reading the status register.
3 RTE Real-time interrupt enable
4 ITE Interval timer interrupt enable
5 CCE Cycle counter interrupt enable
Writing any of the interrupt enable bits to a logic 0 will allow an interrupt condition to be generated when
its corresponding alarm flag is set (see “Interrupts” section).
Control Register
7
6
5
4
3
2
1
0
STOP
AUTO
DSEL
OSC
RO
WPC
WPI
WPR 0201h
START
MAN.
0 WPR Write protect real-time clock/alarm registers
1 WPI Write protect interval timer/alarm registers
2 WPC Write protect cycle counter/alarm registers
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020998
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