DS2404 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2404

EconoRAM Time Chip

Dallas Semiconductor -> Maxim Integrated 

NOTES:

1. All voltages are referenced to ground.

DS2404

2. VIH = 2.0V or VIL = 0.8V with 10 ns maximum rise and fall time.

3. VDQH = 2.4V and VDQL = 0.4V, respectively.

4. Load capacitance = 50 pF.

5. Measured with outputs open.

6. When battery is applied to VBATO input, VCC and VBATB must be 0V.

7. VBATB , or VBATO = 3.0V; all inputs inactive state.

8. Capacitance on the I/O pin could be 800 pF when power is first applied. If a 5kΩ resistor is used to

pullup the I/O line to VPUP , 5 µs after power has been applied, the parasite capacitance will not affect

normal communications.

9. For auto-mode operation of the interval timer, the high level on the I/O pin must be greater than or

equal to 70% of VCC or VBATO .

10. Read and write scratchpad (all 32 bytes) at 3.0V.

11. All other inputs at CMOS levels.

12. VPUP = external pullup voltage.

13. Input load is to ground.

14. An additional reset or communication sequence cannot begin until the reset high time has expired.

15. Read data setup time refers to the time the host must pull the I/O line low to read a bit. Data is

guaranteed to be valid within 1 µs of this falling edge.

16. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always

guarantee a presence pulse.

17. Applies to 1Hz and IRQ pins only.

18. Applies to DQ pin only.

19. Applies to DQ, 1Hz and IRQ pins only.

20. The reset low time (tRSTL ) should be restricted to a maximum of 960 µs, to allow interrupt signaling,

otherwise, it could mask or conceal interrupt pulses.

21. When the battery is attached, the oscillator powers up in the off state.

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