DP80C51 Ver la hoja de datos (PDF) - Digital Core Design
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DP80C51 Datasheet PDF : 10 Pages
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BLOCK DIAGRAM
prgramdatai(7:0)
prgromdatai(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
Opcode
decoder
Program
memory
interface
I/O Port
registers
Timers
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
ea
ale
psen
pswr
External
memory
interface
UART
Interrupt
controller
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
rsto
Control
Unit
Internal
data
memory
interface
User SFR’s
interface
Power
Manage-
ment Unit
DoCD™
Debug Unit
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
ALU
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
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are trademarks of their respective owners.
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL). It
performs the external Program and Data
Memory addressing and data transfers. Pro-
gram fetch cycle length can be programmed by
user. This feature is called Program Memory
Wait States, and allows core to work with dif-
ferent speed program memories.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers. Note that external pins of
this module are connected to appropriate pins
of P3 port.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK peri-
ods when appropriate timer is enabled. In the
counter mode the timer registers are incre-
mented every falling transition on their corre-
sponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock sources for UARTs. Note that external
pins of this module are connected to appropri-
ate pins of P3 port.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) regis-
ters. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
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