● Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
● Scan test ready
● 2.0 GHz virtual clock frequency in a 0.25u
technological process
PERIPHERALS
● DoCD™ debug unit
○ Processor execution control
Run
Halt
Step into instruction
Skip instruction
○ Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE break-
points
○ Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
○ Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
○ Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○ Unlimited number of software breakpoints
Program Memory(PC)
○ Automatic adjustment of debug data transfer
speed rate between HAD and Silicon
○ JTAG Communication interface
● Power Management Unit
○ Power management mode
○ Switchback feature
○ Stop mode
● Interrupt Controller
○ 2 priority levels
○ 2 external interrupt sources
○ 3 interrupt sources from peripherals
● Four 8-bit I/O Ports
○ Bit addressable data direction for each line
○ Read/write of single line and 8-bit group
● Two 16-bit timer/counters
○ Timers clocked by internal source
○ Auto reload 8-bit timers
○ Externally gated event counters
● Full-duplex serial port
All trademarks mentioned in this document
are trademarks of their respective owners.
○ Synchronous mode, fixed baud rate
○ 8-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, fixed baud rate
○ 9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DP80C51 core
can be easy adjusted to requirements of dedi-
cated application and technology. Configura-
tion of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal
type
Program
Memory
- synchronous
- asynchronous
•
Internal Program
Memory size
ROM
-
-
0 - 64kB
•
Internal Program
Memory size
RAM
-
-
0 - 64kB
• Interrupts
-
subroutines
location
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD™ debug unit
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.