CXK5T8512TM Ver la hoja de datos (PDF) - Sony Semiconductor

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CXK5T8512TM

65536-word × 8-bit High Speed CMOS Static RAM

Sony Semiconductor 

Data retention waveform

• Low supply voltage data retention waveform (1) (CE1 contol)

tCDRS

Data retention mode

tR

VCC

2.7V

VIH

VDR

CE1

GND

CE1 ≥ VCC – 0.2V

• Low supply voltage data retention waveform (2) (CE2 contol)

VCC

2.7V

CE2

VDR

Data retention mode

tCDRS

tR

VIL

GND

CE2 ≤ 0.2V

CXK5T8512TM/TN

Data Retention Characteristics

Item

Symbol

Test conditions

Min.

Data retention voltage

VDR

∗1

2.0

Data retention current

ICCDR1 VCC = 3.0V∗1

ICCDR2 VCC = 2.0 to 3.6V∗1

–25 to +85°C —

–25 to +70°C —

+25°C

—

—

Data retention setup time tCDRS Chip disable to data retention mode

0

Recovery time

tR

5

∗1 CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)

∗2 Vcc = 3.3V, Ta = 25°C

(Ta = –25 to +85°C)

Typ. Max. Unit

—

3.6 V

—

12

—

6 µA

0.2

—

0.24∗2 14 µA

—

— ns

—

— ms

–9–

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