CDB4923 Ver la hoja de datos (PDF) - Cirrus Logic

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Fabricante

CDB4923

Multi-Channel Digital Audio Decoders

Cirrus Logic 

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS— I2C® CONTROL PORT

(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol Min

SCCLK clock frequency

(Note 12) fscl

Bus free time between transmissions

tbuf

4.7

Start-condition hold time (prior to first clock pulse)

thdst

4.0

Clock low time

tlow

1.2

Clock high time

thigh

1.0

SCDIO setup time to SCCLK rising

tsud

250

SCDIO hold time from SCCLK falling

(Note 13) thdd

0

Rise time of SCCLK

(Note 14), (Note 18)

tr

Fall time of SCCLK

(Note 18)

tf

Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK

tsca

Time from SCCLK falling to SCDIO valid during read operation

tscsdv

Time from SCCLK rising to INTREQ rising

(Note 15) tscrh

Hold time for INTREQ from SCCLK rising

(Note 16) tscrl

0

Rise time for INTREQ

trr

Setup time for stop condition

tsusp

4.7

Max

400

50

300

40

40

200

(Note

17)

Units

kHz

µs

µs

µs

µs

ns

µs

ns

ns

ns

ns

ns

ns

ns

µs

Notes: 12. The specification fscl indicates the maximum speed of the hardware. The system designer should be

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

13. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by

design and not tested.

14. This rise time is shorter than that recommended by the I2C specifications. For more information, see the

section on SCP communications.

15. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

last data bit of the last byte of data during a read operation as shown.

16. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next

rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat

this condition as a new read transaction. Send a new start condition followed by the 7-bit address and

the R/W bit (set to 1 for a read). This time is by design and is not tested.

17. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull

up value will affect the rise time.

18. This time is by design and not tested.

14

DS262F2

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