CDB4923 Ver la hoja de datos (PDF) - Cirrus Logic

Número de pieza

componentes Descripción

Fabricante

CDB4923

Multi-Channel Digital Audio Decoders

Cirrus Logic 

CS4923/4/5/6/7/8/9

SWITCHING CHARACTERISTICS—SPI CONTROL PORT

(TA = 25 °C; VA, VD = 3.3 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol Min

SCCLK clock frequency

(Note 5) fsck

-

CS falling to SCCLK rising

tcss

20

Rise time of SCCLK line

(Note 11)

tr

-

Fall time of SCCLK lines

(Note 11)

tf

-

SCCLK low time

tscl

150

SCCLK high time

tsch

150

Setup time SCDIN to SCCLK rising

tcdisu

50

Hold time SCCLK rising to SCDIN

(Note 6) tcdih

50

Transition time from SCCLK to SCDOUT valid

(Note 7) tscdov

-

Time from SCCLK rising to INTREQ rising

(Note 8) tscrh

-

Rise time for INTREQ

(Note 8)

trr

-

Hold time for INTREQ from SCCLK rising

Time from SCCLK falling to CS rising

High time between active CS

Time from CS rising to SCDOUT high-Z

(Note 9, 11) tscrl

0

tsccsh

20

tcsht

200

(Note 11) tcscdo

Max

2000

-

50

50

-

-

-

-

40

200

(Note

10)

-

-

-

10

Units

kHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes: 5. The specification fsck indicates the maximum speed of the hardware. The system designer should be

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.

7. SCDOUT should not be sampled during this time period.

8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

second-to-last bit of the last byte of data during a read operation as shown.

9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next

rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat

this condition as a new read transaction. Raise chip select to end the current read transaction and then

drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.

10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull

up value will affect the rise time.

11. This time is by design and not tested.

12

DS262F2

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