CP2400 Ver la hoja de datos (PDF) - Silicon Laboratories
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CP2400 Datasheet PDF : 110 Pages
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CP2400/1/2/3
SFR Definition 15.1. SMBCF: SMBus Clock/Configuration
Bit
7
6
5
4
3
2
1
0
Name
ENSMB
INH
BUSY EXTHOLD SMBTOE SMBFTE
Reserved
Type
R/W
R/W
R
R/W
R/W
R/W
R/W
Reset
(CP2400/2)
0
0
0
0
0
0
0
0
Reset
(CP2401/3)
1
0
0
1
1
1
0
0
Address: 0x68
Bit Name
Function
SMBus Enable.
7 ENSMB This bit enables the SMBus interface when set to 1. When enabled, the interface constantly
monitors the SDA and SCL pins.
SMBus Slave Inhibit.
6
INH
When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus.
SMBus Busy Indicator.
5
BUSY This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
SMBus Setup and Hold Time Extension Enable.
4 EXTHOLD This bit controls the SDA setup and hold times.
0: Setup time is 4 system clocks and hold time is 3 system clocks.
1: Setup time is 11 system clocks and hold time is 12 system clocks.
SMBus SCL Timeout Detection Enable.
3 SMBTOE This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 0 to
reload while SCL is high and allows Timer 0 to count when SCL goes low. The Timer 0 reload
value should be set to overflow the timer after 25 ms.
SMBus Free Timeout Detection Enable.
2 SMBFTE When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for
more than 50 µs.
1:0 Reserved Read = 00b. Must write 00b.
Note: This register has a reset value of 0x00 in devices that do not support SMBus.
Rev. 1.0
107
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