CP2400 Ver la hoja de datos (PDF) - Silicon Laboratories

Número de pieza

componentes Descripción

Fabricante

CP2400

128/64 SEGMENT LCD DRIVER

Silicon Laboratories 

CP2400/1/2/3

14. Serial Peripheral Interface (SPI)

CP2400/2 devices have a 4-wire Serial Peripheral Interface which provides access to the internal registers and

memory. A typical connection to a SPI master is shown in Figure 14.1.

GPIO

Master MISO

Device MOSI

SCK

NSS

GPIO GPIO

INT

MISO Slave

MOSI Device

SCK

NSS

INT

MISO Slave

MOSI Device

SCK

NSS

Figure 14.1. SPI Connection Diagram

14.1. Signal Descriptions

The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below.

14.1.1. Master Out, Slave In (MOSI)

The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used

to serially transfer data from the master to the slave. This signal is always in input for CP2402/1 devices. Data is

transferred most-significant bit first.

14.1.2. Master In, Slave Out (MISO)

The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is

used to serially transfer data from the slave to the master. This signal is always an output for CP2402/1 devices.

Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the slave

select (NSS) signal is de-asserted.

14.1.3. Serial Clock (SCK)

The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to

synchronize the transfer of data between the master and slave on the MOSI and MISO lines. This signal is always

an input for CP2402/1 devices. The SCK signal is ignored when the slave select (NSS) signal is de-asserted.

14.1.4. Slave Select (NSS)

The active-low slave-select (NSS) signal allows support for multiple slave devices on a single bus. It is also used

by the CP2402/1 to detect the start and end of a SPI transfer.

Rev. 1.0

101

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