CP2400/1/2/3
Table 14.1. SPI Slave Timing Parameters
Parameter
Description
Min
TSE
NSS Falling to First SCK Edge
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
2 x TSYSCLK
TSEZ
NSS Falling to MISO Valid
—
TSDZ
NSS Rising to MISO High-Z
—
TCKH
TCKL
SCK High Time
SCK Low Time
5 x TSYSCLK
5 x TSYSCLK
TSIS
TSIH
TSOH
TSLH
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
2 x TSYSCLK
2 x TSYSCLK
—
6 x TSYSCLK
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Max
Units
—
ns
—
ns
4 x TSYSCLK ns
4 x TSYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x TSYSCLK ns
8 x TSYSCLK ns
NSS
T
T
T
SE
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
MISO
T
SEZ
T
SOH
T
SDZ
Figure 14.3. SPI Slave Timing
Rev. 1.0
103