CP2120 Ver la hoja de datos (PDF) - Silicon Laboratories

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CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

CP2120

5.1. Command Set

An SPI Master controls the CP2120 by sending commands across the SPI bus. Some commands initiate I2C

transactions, while other commands modify or monitor CP2120 operation and events.

5.2. Internal Registers

The CP2120 maintains a set of internal registers that can be modified to configure general purpose port I/O and I2C

operation and can be read to obtain device status. Commands reading to and writing from the internal registers can

be issued at any time, even while an I2C transaction is in progress, as they do not initiate any I2C bus transactions.

Table 3 shows a list of all internal registers.

Table 3. Internal Register Addresses

Internal Register

IOCONFIG

IOSTATE

I2CCLOCK

I2CTO

I2CSTAT

I2CADR

RXBUFF

IOCONFIG2

EDGEINT

I2CTO2

Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Section

7

7

6.1

6.1

6.2

6.1

6.3

7

7

6.1

5.2.1. Write to Internal Register

SPI Master

0x20

COMMAND

REGISTER

X

DATA BYTE

A Write to Internal Register command updates the value of one of the CP2120's Internal Registers. A Write to

Internal Register command begins with the command byte, 0x20, followed by the internal register address,

followed by the new value of the internal register. Only one register can be accessed per Write to Internal Register

command.

10

Rev. 1.0

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