CP2105 Ver la hoja de datos (PDF) - Silicon Laboratories

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componentes Descripción

Fabricante

CP2105

SINGLE-CHIP USB TO UART BRIDGE

Silicon Laboratories 

CP2105

Figure 4. QFN-24 Recommended PCB Land Pattern

Table 9. QFN-24 PCB Land Pattern Dimensions

Dimension

Min

Max

Dimension

Min

C1

3.90

4.00

C2

3.90

4.00

E

0.50 BSC

X1

0.20

0.30

X2

2.70

Y1

0.65

Y2

2.70

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

Max

2.80

0.75

2.80

Solder Mask Design

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 m minimum, all the way around the pad.

Stencil Design

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

7. A 2x2 array of 1.10 x 1.10 mm openings on a 1.30 mm pitch should be used for the center

pad.

Card Assembly

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small

Body Components.

Rev. 1.0

11

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