CP2105 Ver la hoja de datos (PDF) - Silicon Laboratories

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CP2105

SINGLE-CHIP USB TO UART BRIDGE

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CP2105

8. GPIO Pins

The CP2105 supports five user-configurable GPIO pins for status and control information. The Standard

Communication Interface (SCI) has three GPIO pins and the Enhanced Communication Interface (ECI) has two

GPIO pins. To use the pins as GPIO pins, the interface with the GPIO pins must be configured in GPIO Mode. By

default, both communication interfaces on the CP2105 are configured for GPIO Mode. If the Modem Control

signals are needed, the interface must be configured for Modem Mode. See Section 7 for more information on

Modem Mode.

Each of these GPIO pins are usable as inputs, open-drain outputs, or push-pull outputs. Four of the GPIO pins also

have alternate functions listed in Table 12 (GPIO.2_SCI does not have an alternate function).

Table 12. GPIO Mode Alternate Functions

GPIO Pin

Alternate Function

GPIO.0_ECI

TX Toggle

GPIO.1_ECI RX Toggle/RS-485 Transceiver Control

GPIO.0_SCI

TX Toggle

GPIO.1_SCI

RX Toggle

By default, all of the GPIO pins are configured as a GPIO input. The configuration of the pins is one-time

programmable for each device. The difference between an open-drain output and a push-pull output is when the

GPIO output is driven to logic high. A logic high, open-drain output pulls the pin to the VIO rail through an internal,

pull-up resistor. A logic high, push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are

typically used when interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the

higher, external voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.

The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as

inputs or outputs are not recommended for real-time signalling.

More information regarding the configuration and usage of these pins can be found in “AN144: CP21xx

Customization Guide” and “AN223: Port Configuration and GPIO for CP210x” available on the Silicon Labs

website.

8.1. GPIO.0-1—Transmit and Receive Toggle

GPIO.0 and GPIO.1 are configurable as Transmit Toggle and Receive Toggle pins for both the Enhanced

Communication Interface and the Standard Communication Interface. These pins are logic high when a device is

not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 when data transfer is in

progress. Typically, these pins are connected to two LEDs to indicate data transfer.

VIO

CP2105

GPIO.0 – TX Toggle

GPIO.1 – RX Toggle

Figure 5. Transmit and Receive Toggle Typical Connection Diagram

14

Rev. 1.0

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