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CAT24WC129

128K-Bit I2C Serial CMOS EEPROM

Catalyst Semiconductor => Onsemi 

CAT24WC129

PIN DESCRIPTIONS

I2C BUS PROTOCOL

SCL: Serial Clock

The features of the I2C bus protocol are defined as

The serial clock input clocks all data transferred into or follows:

out of the device.

(1) Data transfer may be initiated only when the bus

SDA: Serial Data/Address

is not busy.

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA pin

(2) During a data transfer, the data line must remain

is an open drain output and can be wire-ORed with other

stable whenever the clock line is high. Any changes

open drain or open collector outputs.

WP: Write Protect

This input, when tied to GND, allows write operations to

t the entire memory. When this pin is tied to Vcc, the top

r 1/4 array of memory (locations 3000H to 3FFFH) is write

a protected. When left floating, memory is unprotected.

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT24WC129 monitors

the SDA and SCL lines and will not respond until this

condition is met.

ed P Figure 1. Bus Timing

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

tF

tHIGH

tR

tLOW

tLOW

SCL

u tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

tSU:STO

tin SDA IN

SDA OUT

tAA

tDH

tBUF

n Figure 2. Write Cycle Timing

o SCL

Disc SDA

8TH BIT

BYTE n

ACK

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 3. Start/Stop Timing

SDA

SCL

START BIT

Doc. No. 1079, Rev. V

4

STOP BIT

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