CAT24WC129 Ver la hoja de datos (PDF) - Catalyst Semiconductor => Onsemi
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CAT24WC129 Datasheet PDF : 9 Pages
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CAT24WC129
‘dummy’ write operation by sending the START condi- data. The CAT24WC129 will continue to output an 8-bit
tion, slave address and byte addresses of the location it byte for each acknowledge sent by the Master. The
wishes to read. After CAT24WC129 acknowledges, the operation will terminate when the Master fails to respond
Master device sends the START condition and the slave with an acknowledge, thus sending the STOP condition.
address again, this time with the R/W bit set to one. The
CAT24WC129 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
The data being transmitted from CAT24WC129 is out-
putted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24WC129 address bits
so that the entire memory array can be read during one
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC129 sends the initial 8-
t bit byte requested, the Master will respond with an
r acknowledge which tells the device it requires more
a Figure 8. Immediate Address Read Timing
operation. If more than E (where E=16383) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
P S
T
BUS ACTIVITY: A
d MASTER R
T
SDA LINE S
SLAVE
ADDRESS
S
T
DATA
O
P
P
e A
N
C
O
uK
A
C
K
tin SCL
8
9
n SDA
8TH BIT
DATA OUT
NO ACK
STOP
Disco Figure 9. Selective Read Timing
S
T
BUS ACTIVITY: A SLAVE
MASTER R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
A SLAVE
R ADDRESS
T
S
T
DATA
O
P
SDA LINE S
**
S
P
*=Don't Care Bit
A
A
A
C
C
C
K
K
K
A
N
C
O
K
A
C
K
7
Doc. No. 1079, Rev. V
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