Multimedia ICs
1. Master mode, ∗ clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Output data
(HSY, VSY)
BU1424K
Tds1
Fig.11
∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 11
Parameter
Data setup time 1
Symbol Min. Typ. Max.
Tds1
10
—
—
2. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = 2 ∗ input clock (pin 53 = H)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Output data
(HSY, VSY)
Tds2
Fig.12
∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-
lowing the rise of the RSTB pin (pin 52).
Table 12
Parameter
Data setup time 2
Symbol Min. Typ. Max.
Tds2
10
—
—
19