BU1424K Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

Fabricante

BU1424K

NTSC / PAL digital RGB encoder

ROHM Semiconductor 

Multimedia ICs

BU1424K

Table 9: BU1424K color bar input / output data

Input (8-bit hexadecimal for each)

Output (9-bit hexadecimal for each)

RGB24bit

RD GD BD

YUV (4: 2: 2)

YD UD VD

NAME&COLOR

YOUT

COUT

—

—

—

—

—

— SYNC TIP

000

—

—

—

—

—

—

— Color Burst NTSC

—

± 039

—

—

—

—

—

— Color Burst PAL

—

± 03D

—

—

—

—

—

— BLANK LEVEL

—

100

00 00 00 10 80 80 BLACK (Pedestal)

072

000

00 00 FF 28 F1 6D BLUE

092

± 064

00 FF 00 90 36 22 GREEN

117

± 085

00 FF FF A9 A5 10 CYAN

138

± 08E

FF 00 00 51 5A F0 RED

0C6

± 08E

FF 00 FF 6A C9 DD MAGENTA

0E6

± 085

FF FF 00 D2 0E 92 YELLOW

16C

± 064

FF FF FF EB 80 80 WHITE

18C

000

∗ COUT and VOUT display the chrominance amplitude. COUT is 100H ± XXXH.

VOUT is YOUT ± XXXH.

(4) Timing

Table 10 below shows the input and output pins related to timing.

Table 10: BU1424K timing-related input / output pins

Pin No.

52

51

53

27

28

16

22

50

32

33

34

29

Pin name

RSTB

VCLK

CLKSW

VSY

HSY

CDGSWB

NTB

PAL60B

INT

SLABEB

ADDH

PIXCLK

I/O

Function

I

System reset input pin

I

Clock input pin

I

Clock input mode setting pin

I/O

Vertical synchronization signal I / O pin

I/O

Horizontal synchronization signal I / O pin

I

Video-CD / CD-G mode switching pin

I

NTSC / PAL mode switching pin

I

PAL / PAL60 mode switching pin

I

Interlace / Non-interlace mode switching pin

I

Master / Slave mode switching pin

I

Pin which adds 1 line in non-interlace mode

O

1 / 2 divider output for internal clock (OSD clock)

VOUT

000

± 039

± 03D

—

072

± 064

± 085

± 08E

± 08E

± 085

± 064

000

1) Input clocks and input data timings in the various

operation modes

There are slight differences in the input data and the

clock timing, depending on which mode is being used.

18

What is shared by all modes is that, with the BU1424K,

data is read and discharged at the rising edge of the in-

ternal clock. The illustration below shows the input con-

ditions in the various modes.

Share Link: