BU1424K Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

Fabricante

BU1424K

NTSC / PAL digital RGB encoder

ROHM Semiconductor 

Multimedia ICs

BU1424K

∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-

lowing the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as

shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)

Table 14

Parameter

Data setup time 4

Sync signal hold time 2

Sync signal setup time 2

Symbol

Min.

Typ.

Max.

Tds4

10

—

—

Tsh2

10

—

—

Tsd2

10

—

—

BCLK (Internal clock)

HSY (IN / OUT)

PIXCLK

OSDSW

ROSD.GOSD

V,Y,C,OUT

VIDEO-DATA

BLACK YELLOW VIDEO-DATA

Fig.15 Clock timing with the OSD function

∗ The frequency of the PIXCLK pin output is one-half that of the internal clock. This phase is determined at the rising

edge of HSY, as shown in Fig. 15. (In the Encoder Master mode, phase correction is implemented using the HSY

output of the BU1424K itself.) The OSD function is effective only during the time that video output is enabled.

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