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ATTINY40

8-bit Microcontroller with 4K Bytes In-System Programmable Flash

Atmel Corporation 

RAM address given by RAMAR is fetched and written to the destination register within the same

instruction cycle.

Assembly Code Example

RAM_write:

; Set up address (r17) in address register

out RAMAR, r17

; Write data (r16) to data register

out RAMDR, r16

ret

RAM_read:

; Set up address (r17) in address register

out RAMAR, r17

; Read data (r16) from data register

in r16, RAMDR

ret

C Code Example

void RAM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Set up address register */

RAMAR = ucAddress;

/* Write data into RAMDR */

RAMDR = ucData;

}

void RAM_read(unsigned char ucAddress, unsigned char ucData)

{

/* Set up address register */

RAMAR = ucAddress;

/* Read data from RAMDR */

ucData = RAMDR;

}

5.3 I/O Memory

The I/O space definition of the ATtiny40 is shown in “Register Summary” on page 201.

All ATtiny40 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed

using the LD and ST instructions, enabling data transfer between the 16 general purpose work-

ing registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can

be checked by using the SBIS and SBIC instructions. See document “AVR Instruction Set” and

section “Instruction Set Summary” on page 203 for more details. When using the I/O specific

commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.

18 ATtiny40

8263A–AVR–08/10

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