ATTINY20-XUR Ver la hoja de datos (PDF) - Atmel Corporation
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ATTINY20-XUR Datasheet PDF : 219 Pages
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7.4 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled system.
In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as
possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following
modules may need special consideration when trying to achieve the lowest possible power consumption.
7.4.1
Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the analog
comparator is automatically disabled. See “Analog Comparator” on page 105 for further details.
7.4.2
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog
to Digital Converter” on page 109 for details on ADC operation.
7.4.3
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will
contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 31 for details on how to
configure the Watchdog Timer.
7.4.4
Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is
enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the
deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detection” on page
30 and “Software BOD Disable” on page 24 for details on how to configure the Brown-out Detector.
7.4.5
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then
to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input buffers of the
device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the
input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input
Enable and Sleep Modes” on page 46 for details on which pins are enabled. If the input buffer is enabled and the input
signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an
input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital
Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 108 for details.
ATtiny20 [DATASHEET] 25
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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