ATTINY20-XUR Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
ATTINY20-XUR Datasheet PDF : 219 Pages
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CLKPS3
1
1
1
1
1
1
CLKPS2
0
0
1
1
1
1
CLKPS1
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
Clock Division Factor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
At start-up, the CLKPS bits will be reset to 0b0011 to select the clock division factor of 8. The application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum
frequency of the device at the present operating conditions.
6.5.3 OSCCAL – Oscillator Calibration Register
.
Bit
0x39
Read/Write
Initial Value
7
CAL7
R/W
0
6
CAL6
R/W
0
5
CAL5
R/W
0
4
CAL4
R/W
0
3
CAL3
R/W
0
2
CAL2
R/W
0
1
CAL1
R/W
0
0
CAL0
R/W
0
OSCCAL
z Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the
oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving
the factory calibrated frequency as specified in Table 20-2, “Calibration Accuracy of Internal RC Oscillator,” on page 169.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to
frequencies as specified in Table 20-2, “Calibration Accuracy of Internal RC Oscillator,” on page 169. Calibration outside
the range given is not guaranteed.
The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a
setting of 0xFF gives the highest frequency.
ATtiny20 [DATASHEET] 22
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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