ATTINY20-XUR Ver la hoja de datos (PDF) - Atmel Corporation
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ATTINY20-XUR Datasheet PDF : 219 Pages
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Table 6-3. Selection of Main Clock
CLKM1
0
0
1
1
CLKM0
0
1
0
1
Main Clock Source
Calibrated Internal 8 MHz Oscillator
Internal 128 kHz Oscillator (WDT Oscillator)
External clock
Reserved
To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the
CLKMS bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the CLKMS bits with the desired value
6.5.2 CLKPSR – Clock Prescale Register
Bit
0x36
Read/Write
Initial Value
7
6
5
4
3
2
1
0
–
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPSR
R
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
1
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
z Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master
clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in
Table 6-4.
Table 6-4. Clock Prescaler Select
CLKPS3
0
0
0
0
0
0
0
0
1
1
CLKPS2
0
0
0
0
1
1
1
1
0
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8 (default)
16
32
64
128
256
Reserved
ATtiny20 [DATASHEET] 21
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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