AT88SC3216C Ver la hoja de datos (PDF) - Atmel Corporation
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AT88SC3216C Datasheet PDF : 21 Pages
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Table 3. AC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40°C to +85°C, CL = 30pF
(unless otherwise noted)
Symbol
Parameter
Min
Max
Units
fCLK
Async Clock Frequency (VCC Range: +4.5 - 5.5V)
1
fCLK
Async Clock Frequency (VCC Range: +2.7 - 3.3V)
1
5
MHZ
4
MHZ
fCLK
Synch Clock Frequency
0
1
MHZ
Clock Duty cycle
40
60
%
tR
Rise Time - I/O, RST
1
μS
tF
Fall Time - I/O, RST
1
μS
tR
Rise Time - CLK
9% x period
μS
tF
Fall Time - CLK
9% x period
μS
tAA
Clock Low to Data Out Valid
35
nS
tHD.STA Start Hold Time
200
nS
tSU.STA
tHD.DAT
Start Set-up Time
Data In Hold Time
200
nS
10
nS
tSU.DAT Data In Set-up Time
100
nS
tSU.STO
tDH
Stop Set-up Time
Data Out Hold Time
200
nS
20
nS
tWR
Write Cycle Time (at 25° C)
5
mS
tWR
Write Cycle Time (-40° to +85°C)
7
mS
4. Device Operation for Synchronous Protocols
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see Figure 5 on page 8). Data changes
during SCL high periods will indicate a start or stop condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 6 on page 8).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 6 on page 8).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a zero to acknowledge that it has received each word. This
happens during the ninth clock cycle.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1. Clock up to 9 cycles.
6 AT88SC3216C
5014KS–SMEM–08/09
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